REVISTA PERSPECTIVAS

VOL. 8, N˚2 / JULIO - DICIEMBRE 2026 / e-ISSN: 266-6688

Experimental Validation of a Three-Phase

Voltage-Source Inverter with SPWM Modulation

for Low-Voltage Microgrid-Oriented Applications

1,2,3

Electronic and Automation Program Student, Escuela Superior Politécnica de Chimborazo (ESPOCH), Riobamba,

Ecuador

GITEA Research Group, Escuela Superior Politécnica de Chimborazo (ESPOCH), Riobamba, Ecuador

RESUMEN

This work presents the design, implementation,

and experimental validation of an open-loop

three-phase inverter prototype. The experimental

campaign was carried out with a regulated 48

V DC bus, while the bus-monitoring circuit

was dimensioned for a wider voltage range.

Control was implemented on an STM32 using

digital SPWM, with a 120° phase shift and an

adjustable output frequency between 60 and 80

Hz. To reduce the risk of cross-conduction in the

MOSFETs, dead-time insertion was conﬁgured in

both hardware and ﬁrmware. Tests with resistive

loads veriﬁed three-phase operation in star and

delta conﬁgurations, with balanced line voltages

under laboratory conditions. The eﬃciency

close to 92% corresponds to the tested low-load

condition. Characterization at higher power

levels and harmonic-distortion measurements are

proposed as the next validation stage.

Keywords: Dead-time, Energy Eﬃciency,

MOSFET, SPWM Modulation, Three-phase

Inverter.

Validación experimental de un inversor trifásico

de fuente de voltaje con modulación SPWM para

aplicaciones de baja tensión orientadas a microrredes

ABSTRACT

Este trabajo presenta el diseño, la implementación

y la validación experimental de un prototipo de

inversor trifásico en lazo abierto. La campaña

experimental se realizó con un bus DC regulado

de 48 V, mientras que el circuito de monitoreo

del bus fue dimensionado para un rango mayor de

tensión. El control se implementó en un STM32

mediante modulación SPWM digital, con desfase

de 120° y frecuencia de salida ajustable entre 60

y 80 Hz. Para reducir el riesgo de conducción

cruzada en los MOSFETs, se conﬁguró inserción

de tiempos muertos en hardware y ﬁrmware. Las

pruebas con cargas resistivas permitieron veriﬁcar

la operación trifásica en conﬁguraciones estrella

y delta, con tensiones de línea balanceadas bajo

las condiciones de laboratorio. La eﬁciencia

cercana al 92% corresponde a la condición de

baja carga ensayada. La caracterización a mayor

potencia y la medición de distorsión armónica se

plantean como la siguiente etapa de validación.

Palabras Clave: Dead-time, Eﬁciencia

Energética, MOSFET, Modulación SPWM,

Inversor Trifásico.

Fecha de Recepción: 03 Julio 2026 · Fecha de Aceptación: 22 Julio 2026 · Fecha de Publicación: 30 Julio 2026

mario.fuela@espoch.edu.ec

carlos.jarat@espoch.edu.ec

kevin.barrionuevo@espoch.edu.ec

wilian.guaman@espoch.edu.ec

Mario Fuela-Uvidia

Kevin Barrionuevo-Lara

Carlos Jara-Toaza

Wilian Guamán-Cuenca.

REVISTA PERSPECTIVAS

VOL. 8, N˚2 / JULIO - DICIEMBRE 2026 / e-ISSN: 266-6688

https://doi.org/10.47187/perspectivas.8.2.265

REVISTA PERSPECTIVAS

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I. Introducción

II. Metodología

The conversion of direct current (DC) energy

into three-phase alternating current (AC) is a

fundamental process in power electronics [1],

particularly for supplying loads from low-voltage

48 V DC buses [2]. During this conversion

process, one of the most critical challenges in

bridge inverter topologies is preventing cross-

conduction between switching devices. To

avoid this short circuit, it is essential to design

algorithms that inject precise dead-times,

considering that an incorrect conﬁguration can

severely distort the output voltage [3].

Due to its ease of implementation, SPWM

modulation remains one of the main methods

for controlling three-phase inverters and

transforming switching signals into alternating

voltage using six transistors. As demonstrated

by previous work on MOSFET-based inverters

coupled to star-connected loads, the key to

obtaining an optimal output voltage lies in the

precise design of the switching patterns and

maintaining grid balance [4].

Recent works have shown the relevance of

studying the behavior of inverters under

real operating conditions and the possible

degradation of power devices. In [5], the eﬀect

of variations in the on-state resistance of

MOSFETs on phase imbalance, total harmonic

distortion, and the stability of a three-phase

inverter is analyzed, using a validation strategy

based on MIL, SIL, and PIL on an STM32

platform. Likewise, [6] presents a hybrid DC/

AC conversion topology with modiﬁed SPWM

modulation, inherent protection against shoot-

through, and experimental validation in a low-

power prototype.

In this context, the present work focuses on the

design, implementation, and laboratory validation

of an open-loop SPWM three-phase inverter,

with dead-time insertion and tests on balanced

resistive loads in star and delta conﬁgurations.

The development of the three-phase inverter

was structured based on an analytical and

modular design, dividing the system into control,

power, and validation stages. The prototype

was dimensioned to operate at low voltage. The

experimental validation was carried out using a

regulated DC bus close to 48 V, while the bus

measurement circuit was designed with suﬃcient

margin for nominal and overvoltage conditions.

Based on these speciﬁcations, the load capacity

and the protection elements against thermal and

voltage transients were dimensioned.

Table I. Design parameters and test conditions

Parameter Symbol Value used

Bus DC de

ensayo

) 48.87 V

DC bus sensing

range

— 0–50 V DC

PWM switching

frequency

) 3 kHz

Dead-time

) 1.5 (μs)

Output

frequency

) 60-80 Hz

Modulation

technique

— SPWM

Power devices

— 6 MOSFETs

IRFP460A

Gate drivers

— IR2010

Load type

— Resistive

Nominal load

resistance

) (≈620 Ω)

Load

connection

— Star / Delta

Measured

current per

branch

)

33.65 mA

Input power

) 6.793 W

Calculated

output power

out

) 6.3156 W

Experimental

eﬃciency

(η) 92.97 %

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Fig. 1: Block diagram of the three-phase inverter architecture and

power ﬂow.

To summarize the design parameters and the

conditions used during the experimental tests,

Table I presents the main operating variables of

the three-phase inverter. These values include

the DC bus, the switching frequency, the dead-

time, the load conﬁguration, and the electrical

quantities recorded for the power and eﬃciency

calculations.

A. General System Architecture

The converter topology is based on a three-leg

inverter bridge architecture. Fig. 1 illustrates

the general block diagram of the implemented

system. For energy conversion, a classical

inverter bridge topology was implemented. The

component-level design is detailed in Fig. 2,

which shows the electrical schematic with the

half-bridge conﬁguration for each of the three

phases.

The system is powered by a stabilized DC

power supply. The control stage calculates the

switching patterns and sends PWM logic signals

to the power stage. These signals are received by

IR2010 gate drivers, which act as high-side/low-

side drivers to condition the ﬁring levels required

by the six MOSFETs in the inverter bridge.

Finally, the energy converted into three-phase

alternating current is applied to the resistive load

bank used for validation.

B. Firmware Development and Programming

Environment

For the synthesis of Sinusoidal Pulse Width

Modulation (SPWM) and the rigorous injection

of dead times, the digital control was centralized

in a 32-bit STM32 microcontroller with an ARM

Cortex-M4 core (NUCLEO-F401RE board) [7].

Firmware programming, compilation and

debugging was done in STM32CubeIDE.

The generation of the SPWM signals was

implemented using the advanced TIM1 timer,

conﬁgured to operate with a switching frequency

of 3 kHz and complementary outputs, avoiding

software delays. The use of complementary

channels allows the 1.5 μs dead-time timing to be

concentrated on the microcontroller peripheral

and reduces dependence on the ﬁrmware

execution time [7], [8].

In addition, due to the digital nature of the

modulation programmed in the STM32, the

fundamental output frequency (f

) is not limited

to 60 Hz. The system allows this frequency to

be dynamically adjusted simply by modifying the

timer parameters in the ﬁrmware. This ﬂexibility

gives the prototype the ability to adapt to 50

Hz grids or to operate in variable-speed motor

applications, without requiring any modiﬁcation

to the power hardware.

Fig. 2: Electrical schematic of the power stage of the three-phase

inverter.

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C. Nominal Power Capacity

To deﬁne the operating range of the system, the

energy transfer capacity was analyzed, assuming

an expected line-to-neutral RMS voltage of 120

rms

per phase and a continuous load current

=5 A. Under these boundary conditions, the

apparent power (S) supported by each phase of

the inverter is determined by (1):

For real application scenarios involving inductive

loads, a standard power factor of 0.8 is assumed.

Consequently, the nominal active power (P)

delivered by the power stage is calculated using

(2):

These values deﬁne the thermal and conduction

safety limits considered for selecting the

semiconductor devices.

D. Design of the Snubber RCD Network

The parasitic inductances of the printed circuit

board and wiring induce severe transient

overvoltages (dv/dt) during the fast turn-oﬀ

periods of the transistors. To absorb the reactive

energy and limit voltage peaks, an RCD snubber

network was designed and implemented in

parallel with each semiconductor device [9].

The analytical dimensioning was carried out

by extracting the dynamic parameters from the

IRFP460A MOSFET datasheet [10] A fall time

of t

= 39 ns and a maximum continuous current

of I

=20 A at 25 °C, were considered, operating

under a drain voltage of V

= 170V and the

nominal load current of I

= 5 A.

The minimum value of the snubber capacitance

) must guarantee a safe voltage level until the

device current decreases to zero, and is calculated

using (3):

The network resistance (R

) serves a dual

purpose: limiting the peak discharge current of

the capacitor through the transistor during turn-

on and allowing its complete discharge during

the active duty-cycle. The minimum resistive

value is obtained using (4):

In turn, the maximum resistance limit is

restricted by the minimum turn-on time T

ON(min)

At a switching frequency of 10" kHz" (period of

100 μ"s" ) and assuming a minimum duty cycle

of 1%, T

ON(min)

is equivalent to 1 μ"s" . Assuming

a commercial snubber capacitance of 1" nF" , the

upper limit is deﬁned by (5):

Based on the calculated envelope (11.33 Ω≤R_

s<333.3 Ω), commercial resistors from 47 Ω to

100 Ω were selected, since the residual power in

the resistor per cycle, analytically evaluated, was

0.083" W" .

E. Signal Conditioning and DC Bus

Measurement

For real-time monitoring and system protection,

a signal conditioning circuit was implemented,

allowing the microcontroller to read the physical

voltage of the DC bus while logically isolating

voltage peaks. A resistive voltage divider was

designed to scale the high-voltage levels, (170"

V" nominal and 220" V" under overvoltage

conditions) to the logical operating range of

the microcontroller analog-to-digital converter

(ADC) which has a maximum reference of 3.3 V

and a 12-bit resolution.

To standardize the design and withstand power

dissipation, the upper branch ( R

top

) was built

using a series arrangement of three 332" k" Ω

axial resistors rated at 3/4" W" , while the lower

branch (R

bot

), connected to physical ground, was

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III. Results

To safely validate the SPWM control logic, the

phase shift between phases, and the behavior

of the designed inverter bridge, a reduced-scale

experimental test bench was implemented in the

laboratory. The nominal bus was supplied by a

regulated source stabilized at 48.87" V DC" and

the inverter was operated in open loop coupled

to a bank of resistive loads (incandescent lamps)

conﬁgured in Star and Delta to evaluate the

balance of the generated network. The physical

assembly of this system, integrating the digital

control stage and the power bridge, is illustrated

in Fig. 3.

set to 10 kΩ. The scaled voltage (V

out

) entering

the PA1 pin of the microcontroller is governed

by (6):

This conﬁguration provides a constant scaling

ratio of 0.00994. The conversion to the continuous

digital domain by the 12-bit ADC (whose values

range from 0 to 4095) is analytically deﬁned in

Table II, establishing the logical thresholds for

calibration, safe low-voltage operation, and the

nominal tolerance limit.

Table II. Voltage behavior and adc mapping

Voltage

(DC Bus)

Scaled

Voltage

(Vout)

Digital Value

Read (ADC)

Operating

Scenario

0" V"

(Oﬀ)

0.000" V" 0 Zero

calibration

48" V"

(Tests)

0.477" V" ≈592

Low-

voltage

validation

170" V"

(Nominal)

1.690" V"

≈2097 Nominal

operation

220" V"

(Overvoltage)

2.186" V" ≈2713 Safety limit

A. SPWM Algorithm and Phase Shift

Validation

The primary evaluation consisted of verifying

the switching signals generated by the STM32

microcontroller before their injection into

the power stage. Using an oscilloscope, it

was conﬁrmed that the developed algorithm

successfully synthesized three sinusoidal

envelopes with a phase shift of 120^ electrical

degrees.

In Fig. 4 shows the three SPWM phase signals

recorded during the experimental validation. A

vertical oﬀset was applied only for visualization

Fig. 3: Physical prototype of the three-phase inverter

Fig. 4: Experimental three-phase SPWM signals showing the (120^)

electrical phase shift.

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purposes, allowing the phase relationship between

the signals to be observed more clearly. The

waveforms conﬁrm the (120^) electrical phase

shift between phases A, B, and C, validating the

synchronization of the digital SPWM algorithm.

The fundamental output frequency remained

stable (period of 16.66ms). In addition, the

action of the dead-time safety band was visually

veriﬁed, showing that the complementary signals

did not overlap at any time. This conﬁrmed the

absence of signal overlaps and prevented the

shoot-through phenomenon under the established

test conditions. Under the Star (Y) load

conﬁguration, the diﬀerential voltage measured

at the neutral point remained close to zero, and

the line-to-line voltage waveforms were recorded

at the output terminals, conﬁrming the symmetry

of the three-phase bridge.

As observed in Fig. 5, the measured signal

corresponds to an unﬁltered line-to-line PWM

voltage. The envelope associated with SPWM

modulation is identiﬁed from the variation in

pulse width, while the ﬁnal voltage waveform

across the load depends on the harmonic content

and the impedance seen by the inverter. The

ﬁgure veriﬁes the modulation logic and the phase

shift between phases under the test conditions.

Although the total harmonic distortion (THD)

was not experimentally measured in this

stage, the selected switching frequency allows

a preliminary theoretical estimation of the

harmonic distribution. Considering a switching

frequency of (f

s=3,kHz

) and a fundamental output

frequency of (f

o=60,Hz

), the frequency modulation

Fig. 5: Line-to-line output voltage waveform V_AB, under SPWM

modulation.

ratio is given by (m

=3000/60=50). This

indicates that the dominant harmonic components

associated with the SPWM switching process are

expected to be concentrated around the carrier

frequency and its sidebands. Therefore, since the

output voltage was measured without a ﬁltering

stage, future work should include experimental

THD measurements and the design of an LC

or LCL output ﬁlter to attenuate switching

harmonics and improve the power quality of the

inverter output, considering harmonic control

criteria such as those established in IEEE 519-

2022 [11].

B. Power and Energy Eﬃciency

Analysis

To evaluate the electrical and energy performance

of the physical prototype, the input and output

powers were measured during continuous

operation with resistive loads. The power factor

assumed for the incandescent lamps used in the

test was unity.

In the direct current stage, the instrumentation

recorded the bus voltage and the input current

under steady-state conditions. Based on these

data, the total input power consumed by the

system was determined using (7):

In the alternating current stage, the line-to-line

voltages (V

) were measured across the resistive

loads, and the current associated with the test

was recorded. Using the average voltage value

and the measured current, the three-phase active

output power was calculated using (8):

Finally, the overall eﬃciency of the converter

under these experimental conditions was

estimated from the power ratio indicated in (9):

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C. Discussion of Eﬃciency and Fixed Losses

The experimental eﬃciency obtained by the

prototype was 92.97% under low-voltage and low-

load laboratory conditions. This value should not

be interpreted as the maximum rated eﬃciency

of the inverter, since the system was evaluated in

open-loop operation, with purely resistive loads,

without an output ﬁlter, and operating below its

rated power capacity.

The result obtained is consistent with

otherstudies on low-power three-phase inverters.

For instance, Lujara reported experimental

eﬃciencies that did not fall below 92%, with

values ranging approximately from 92.1% to

94.9%, depending on the load condition [12].

In comparison, more optimized topologies,

such as multilevel or transformerless inverters,

typically exhibit eﬃciencies exceeding 96%

under diﬀerent operating, power, and control

conditions [1]. Therefore, the performance

diﬀerence is primarily associated with the power

level, the employed topology, the presence of

ﬁltering stages, and the control strategy. In this

context, the 92.97% eﬃciency achieved during

the tests conﬁrms the adequate performance of

the prototype under the evaluated experimental

conditions, considering that the hardware-based

dead-time insertion prevented cross-conduction

between complementary signals and ensured the

safe operation of the power stage. Nevertheless,

elements such as the control board, gate drivers,

cooling system, and the switching process

represent inherent power consumptions and

losses associated with the system's operation. For

this reason, additional tests at higher load levels

are required to determine the eﬃciency trend of

the inverter under conditions closer to its rated

operating point.

III. Conclusiones

The obtained results made it possible to verify

the generation of three modulated signals with

a 120° electrical phase shift, conﬁrming the

functionality of the developed ﬁrmware to

produce a balanced three-phase system at low

voltage. The dead-time insertion prevented

overlap between complementary signals and

protected the semiconductors during switching

operations. The prototype operated stably during

the tests with resistive loads in star and delta

conﬁgurations. The measurements showed line

voltages with close values and balanced behavior

under the considered laboratory conditions.

During the low-load tests, the prototype achieved

an eﬃciency close to 92%. This result is

inﬂuenced by the system’s internal consumption

when the transferred power is reduced. The energy

characterization must be completed with tests at

higher load levels and with an explicit deﬁnition

of the voltage and current magnitudes used in the

calculation. As future work, the inverter should

be validated at higher load levels, total harmonic

distortion (THD) measurements should be

incorporated, its performance with inductive

loads or three-phase motors should be evaluated,

and ﬁltering, interconnection, and power quality

criteria should be analyzed if the prototype is

oriented toward microgrid applications.

IV. Referencias

[1] M. K. Hossain, P. Chowdhury, I.

Nowshin, M. R. Islam, A. Al-Hysam, y O. Farrok,

«Grid-connected inverter for photovoltaic energy

harvesting: Advances in topologies and control

techniques», 1 de enero de 2026, Elsevier Ltd.

doi: 10.1016/j.ecmx.2025.101422.

[2] D. Kumar, F. Zare, y A. Ghosh, «DC

Microgrid Technology: System Architectures,

AC Grid Interfaces, Grounding Schemes, Power

Quality, Communication Networks, Applications,

and Standardizations Aspects», IEEE Access,

vol. 5, pp. 12230-12256, jun. 2017, doi: 10.1109/

ACCESS.2017.2705914.

[3] D. Chatterjee, C. Chakraborty, y S.

Dalapati, «An Overview on Dead-Time Distortion

and Its Correction in PWM Inverters», 2025,

Institute of Electrical and Electronics Engineers

Inc. doi: 10.1109/OJPEL.2025.3600262.

[4] E. Can y H. H. Sayan, «SSPWM

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THREE PHASE INVERTER DESIGN AND

EXPERIMENTED ON UNBALANCED

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[5] O. Idbouhouch, M. Zegrari, N. Rabbah,

I. A. Abdelmoula, H. Oufettoul, y S. Motahhir,

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10.1016/j.rineng.2025.105227.

[6] M. S. Rana, M. A. Abedin, W. Hassan, M.

A. Hossain, y A. Hossain, «A SEPIC-Ćuk derived

hybrid converter with single-input inductor and

dual DC/AC outputs for microgrid applications»,

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[7] «STMicroelectronics, NUCLEO-

F401RE: STM32 Nucleo-64 development

board with STM32F401RE MCU». [En línea].

Disponible en: www.st.com

[8] «STMicroelectronics, AN4776:

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microcontrollers, Application Note, Rev. 4.»,

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[9] N. M. O W, T. M. Undeland, W. P.

Robbins, y J. Wiley, «POWER ELECTRONICS

Converters, Applications, and Design THIRD

EDITION», 2003. (Note: Chapter 27 of this

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networks.)

[10] «IRFP460A Vishay Siliconix»,

Accedido: 21 de junio de 2026. [En línea].

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[11] 519-2022 - IEEE Standard for Harmonic

Control in Electric Power Systems. IEEE, 2022.

[12] N. K. Lujara, “Three Phase PWM Inverter

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[14] Remus. Teodorescu, Marco. Liserre,

y Pedro. Rodríguez, Grid converters for

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